Overview

Peripherals — tile area follows register count, colour follows the share of registers verified.

Instructions by family

verified: a test with an oracle ran it. exercised only: only fuzzing or firmware ran it, nothing asserted its result. never run: no test executed it. Click a chip for its specification reference.

Encoding space

One pixel per encoding, so the gaps in the decoder's input space are visible. Dark = not an instruction in the catalogue and never run; blue = run although no catalogue entry matches (reserved and undefined probes). An instruction counts as verified once any one of its encodings ran under an oracle test, so these maps are stricter than the chips above: most of the space is only swept, not asserted.

PIO MOV matrix

Destination × source for each operation (none, invert ~, bit-reverse ::), datasheet 11.4.10.

Peripheral registers

One square per register in address order. A register is verified when both directions it supports were exercised by oracle tests (reset value, round trip, access type).

Datasheet sections cited by tests

Every section of the chapters on the processor subsystem, PIO and peripherals. Colour is the number of tests that cite the section in [Trait("Spec", …)] (red 0, amber 1–2, green 3 or more). This measures traceability to the datasheet, not behavioural completeness.